As technology nodes shrink, in some integrated circuit (IC) designs, there has been a desire to replace the common polysilicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. One process of forming a metal gate structure is termed a “gate last” process in which the final gate structure is fabricated “last” which allows for reduced number of subsequent processes, including high temperature processing, that are to be performed after formation of the gate.
However, there are challenges to implementing such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. As the gate width and space between devices decrease, these problems are exacerbated. For example, in a “gate last” fabrication process, it is difficult to achieve a low gate resistance for a semiconductor device because voids are generated in the metal gate electrode after metal layer deposition for gap filling of a high-aspect-ratio trench, thereby increasing the likelihood of device instability and/or device failure.